The present invention relates to a test circuit, an integrated circuit, and a test method.
Attention has recently been focused on the proposal of the universal serial bus (USB) 2.0 standard which can implement data transfer at speeds far greater than the prior-art USB 1.1 standard, while maintaining backward compatibility with USB 1.1. The USB 2.0 transceiver macrocell interface (UTMI), which has defined interface specifications for parts of the physical-layer and logical-layer circuits under USB 2.0, has also been proposed. A prior-art technique of using macro blocks (macro cells) conforming to UTMI in an integrated circuit is disclosed in Japanese Patent Laid-Open No. 2002-343864, by way of example.
In addition to the full-speed (FS) mode defined by the prior-art USB 1.1, USB 2.0 provides a transfer mode called high-speed (HS) mode. Since data transfer in this HS mode is at 480 Mbps, it is possible to implement data transfer at a much higher speed than the data transfer at 12 Mbps of FS mode.
With such a UTMI macro block that is capable of high-speed data transfer, however, there is a technical problem in that it is difficult to test to detect faults. In other words, transmission and reception processing occurs between the UTMI macro block and a serial interface engine (SIE) in the previous stage, over an 8-bit bus at a 60-MHz clock frequency (a first clock frequency), by way of example. To detect faults (such as wiring defects and element defects) in the UTMI macro block, therefore, it is necessary for an external tester to write a transmission data signal at the 60-MHz clock frequency and read a reception data signal at the 60-MHz clock frequency, from a test terminal (pin). However, the test terminal has a large parasitic capacitance so that there are large signal delays in the I/O cell of the test terminal. This means that attempts to perform tests at a high-speed clock frequency of 60 MHz result in large mismatches between the test results and expected values, leading to fears that it would be impossible to implement stable testing.
A UTMI macro block causes particular concern in that it creates a special situation because the internal analog circuit and high-speed digital circuit cannot operate in HS mode without being set to a clock frequency of 480 MHz (60 MHz). Without testing at 480 MHz (60 MHz), it is impossible to guarantee high-speed operation in HS mode and thus there is a danger that reliability will deteriorate.